Browsing by Author "Bakkes, P. J."

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    A reconfigurable array processor
    (Stellenbosch : Stellenbosch University, 1996-03) Bakkes, P. J.; Stellenbosch University. Faculty of Engineering. Dept. of Electrical and Electronic Engineering.
    ENGLISH ABSTRACT: This dissertation reports on an investigation of the trade-off of the properties of presently available fixed and reconfigurable logic to find an optimal use for both types of logic in a typical engineering application. The research vehicle is a 32 bit floating point matrix-vector array processor. The system named MIX is designed, simulated, built and tested and the results are evaluated. Simulation and synthesis tools are used to extensively and a firm base for further research is established. State machines are implemented with a shift register technique developed earlier by the author. The results prove that fixed logic is most suited for subsystems such as memories and floating point units where reconfiguration is not necessarily required, but high logic density and speed are essential. Reconfigurable logic proves most useful for control functions and simple data manipulation. Delays resulting form the routing of data through the reconfigurable logic, as hidden by using pipeline techniques. It is proven that the performance of a mixed logic system approaches that of a pure fixed logic implementation, if the design allows the overlap of the execution of functions in the fixed and reconfigurable subsystems.